Xilinx zcu102 ethernet price

Xilinx zcu102 ethernet price. **BEST SOLUTION** Hi @illaumeguilla1 ,. While doing this, I drove using the PHY chip on the board and did the test from the RJ45 input. Please double check. I did try to search the forum but only got some nearly answers, so I'll ask my questions anyway. bsp . 1 x4 based on Intel I350. My problem is that I am not able to make an ethernet connection between the PC and the board. dtsi file from 2) I was able to transmitt some dummy RAW ethernet packets with only pcs/pma ip core configured in SGMII mode in TRIMAC and PS MAC mode both and was successfully viewing the dummy packets in wireshark with 1000 Mbps rate. I have a Zynq ZC706 design that I'm porting to the ZCU102. 4 PetaLinux - 2015. Is there special configuration needed to allow enumeration to occur? Communication between PS and PL ethernet of ZCU102. Hello, I am a newbie for Petalinux. 0). This was created in 2016. Click Generate bitstream. I am designing a custom board that is based on Xilinx's ZCU102 development board and have a question regarding the DP838671IR Ethernet PHY strapping pins. com) It is for fixed link, but the required property here is "is-internal-pcspma". You can right click on any Xilinx IP and create an example project which also includes a testbench. inet6 addr: ::1%4879712/128 Scope:Host. After the petalinux is booted successfully, it seems the OS does not recognized the device (ZC706). You should be using ZCU102 production board and BSP. vivado -source * top. ) on how to use Ethernet in ZCU102 board? Dec 9, 2021 · Thanks for your reply. I am not really sure about every connection, so please advice me if anybody find an issue. I successfully build SD card image, enabled PCI in kernel, at DTB was enabled PCI interface and set some GPIO (I'll explain later). I have the 10G/25G subsystem (2. Number of Views 65 Number of Likes 0 Number of Comments 4. rev 1. GT subcore in example design. After generating an image from petalinux 2017. bsp". Oct 19, 2023 · Vivado™ ML 2023. 150643] xilinx_axienet 80010000. Just like here, I want to drive the phy chip on the board in ZCU102 and use the RJ45 input (RJ45 is not necessary, it can be done I am working to implement an Ethernet link on ZCU102, by using the. 351152] xilinx_axienet 80030000. 1. Thanks. The PCIe card I am using is "HPE Ethernet 1Gb 4-port 366FLR Adapter", which is PCI Express 2. The design, should be more or less sound, as on 2 of 3 ZCU102 boards I have at disposal, everything works just fine. I have try to use ethernet connection defined by gem3 RGMII. I followed the tutorial ug1209 to run the hello world application from ARM Cortex A53, but the message never get printed and i get the info " Info: Cortex-A53 #0 (target 10) Running " on the XSCT I have two ZCU102s with a petalinux 2017. [ 48. This will generate a Vivado project for your hardware platform. 2. I am thoroughly confused by XAPP1305. Ethernet PHY to loopback mode in Xilinx ZCU102. 99/24. The core is designed to work with the latest UltraScale™ and UltraScale+™ FPGAs. I have a ZCU102. 1, i follow all users guide to bring up the board; preprare a QSPI boot image and all working fine. $ petalinux-create -t project –template zynqMP -s xilinx-zcu102-v2021. And then we added the device tree below. ethernet eth1: XXV MAC block lock not complete! Cross-check the MAC ref clock configuration The Mac is getting its "gt_ref_clk" clock from pins C7/C8, and is configured to accept 156. Hi, I am working to implement an Ethernet link on ZCU102, by using the 1G/10G/25G Switching Ethernet Subsystem IP version 2. There is this wiki page on Zynq MPSoC Ethernet. Does anyone know if/when Xilinx might update the reference ZCU102 SFP and 1G/2. tcl; which opens the gui. PS EMIO and MIO etherrnet on zcu102. There's no boot log messages for this interface, other than the expected "xilinx_axienet 80010000. I attach the block diagram I am using. The ZCU102 Evaluation Kit enables designers to jumpstart designs for Automotive, Industrial, Video and Communications applications. 6 Gbps |1. The test message is as follows: root@MPSOC_SYNC:~# ptp4l -i eth0 -s -m. ethool for eth1 has ptp0 as hardware clock. The idea is to establish contact between PL and PS of 2 Boards. Xilinx I ran the "AXI 1G/2. Waiting for PHY to complete autonegotiation. renderer: networkd. So they are referring to different IPs. IIC PHY reset on ZCU102 successful. 979275] pci 0000:00:00. Admin Note – This thread was edited to update links as a result of our community migration. 3> and is being run in <2018. The system boot correctly but the ethernet interface is not detected. You also have the option to QSFP to SFP+. I have downloaded the 1G PL Ethernet files from https 1 answer. Have anyone used Ethernet Cores and configured the board using FPGA remote programming tool. Net: ZYNQ GEM: ff0b0000, mdio bus ff0b0000, phyaddr -1, interface rgmii-id. 5G Ethernet subsystem IP core [Ref 1]. The 1000BASE-X/SGMII PHY and the GTH transceiver are a part of the AXI Ethernet core for 1G PL Ethernet link, which uses the AXI 1G/2. I also want to add MIO ethernet. Can you have a look at the attached zip. Faster device image generation with multi-threaded support. Increase performance of designs in Versal Premium and Versal HBM devices with automatic place & route of SLR crossings. Right now they have the same MAC address. Michal Simek < michal. Mar 9, 2020 · ZCU102 evaluation board; AC power adaptor (12 VDC) USB Type-A to USB Mini-B cable (for UART communication) USB Type-A to USB Micro-B cable (for JTAG access) Xilinx Tools Version: Vivado 2017. Programmable Logic, I/O and Packaging. (I have reference documents XAPP1305 Ethernet Subsystem) I create a project to implement loopback on 2 SFP+ ports of the board , with IP Core Trans_Rev_Data_10G is responsible for pushing ethernet packet II to Port 0 and loopback to port 2 (image Feb 3, 2022 · The most obvious difference is below: 2017. 3) I looked into pcs/pma user document, in MAC mode using speed_100, speed_10_100 bit configured the pcs/pma/sgmii ip in Network access to linux booted on ZCU102. My IP block, largely taken from the TRM, would be something like Currently I am working with the 10G/25G Ethernet Subsystem on the ZCU102 board (Vivado 2018. Hi For a customer project, i need to use a ZYNQ US+. IP and Transceivers. This kit features a Zynq™ UltraScale+™ MPSoC with a quad-core Arm® Cortex®-A53, dual-core Cortex-R5F real-time processors, and a Mali™-400 MP2 graphics processing unit based on 16nm FinFET+ May 31, 2019 · AMD / Xilinx MPSoC ZCU102 Evaluation Kit features a Zynq UltraScale+ MPSoC device with a quad-core Arm® Cortex-A53, dual-core Cortex-R5 real-time processors, and a Mali-400 MP2 graphics processing unit based on AMD / Xilinx's 16nm FinFET+ programmable logic fabric. I am trying to build the 10G Eth PL reference design (XAPP1305). ZCU102 acts as the slave of 1588 and uses commands (“ ptp4l -i eth0 -s -m ”) to test, but we will get high values of master offset, frequency and path delay as a result. This kit features a Zynq™ UltraScale+™ MPSoC with a quad-core Arm® Cortex®-A53, dual-core Cortex-R5F real-time processors, and a Mali™-400 MP2 graphics PC to ZCU102 Ethernet connection. I'm proceeding with a 1G design for now with the hope that I hear something about 10G at which point I'll upgrade my design. 10G between two ZCU111 boards works fine. This kit features a Zynq™ UltraScale+™ MPSoC with a quad-core Arm® Cortex®-A53, dual-core Cortex-R5F real-time processors, and a Mali™-400 MP2 graphics processing unit based on 16nm FinFET+ Product Description. x release. Subject: Describes how to set up and run the BIST test for the ZCU102 evaluation board. 3). eth0: ethernet@ff0b0000. 2, but should still help 10G Ethernet Performance with ZCU102 board using XAPP1305 solution. 3. Upon reviewing the instructions, i am following them exactly. I get lot of CRC errors. 5G Ethernet Subsystem (7. 1 ethernet. 该套件具有基于 AMD 16nm FinFET+ 可编程逻辑架构的 Zynq™ UltraScale+™ MPSoC 器件，提供一款四核 ARM® Cortex®-A53、双核 Cortex-R5F 实时处理器以及一款 Mali™-400 MP2 图像处理单元 Network load 10%. And we Build PetaLinux System Image in ZCU102, the image also imports LinuxPTP and ethtool. One difference between the IP in the designs is that in the ZC706 there was a gtrefclk_bufg_out output whereas this output doesn't exist in the ZCU102 version. Jul 22, 2020 · ZCU102 evaluation board. suhas99hv (Member) asked a question. But I don´t have any LOC constraints defined for my ZCU102 board. 1, ethtool version is 4. Xilinx advertises the following results for 1500 MTU. This allowed the board to access the internet, but I would prefer to connect the board through the PC because I use the port for another device. I tried changing the mac in petalinux-config, but that didn't work. Title: Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit Quick Start Guide (XTP426) Author: Xilinx, Inc. I'm facing some issues with 10G ethernet running on ZCU102 board. 0. However, on one of the boards, during (peta)linux boot, kernel reports DMA reset timeout. . And yes, our core supports full duplex. version: 2. dtsi (attached). there is a tutorial on how to use the 10G AXI Ethernet on the ZCU102. Currently I am working with the 10G/25G Ethernet Subsystem on the ZCU102 board (Vivado 2018. I am getting very poor performance results for TCP or UDP. This kit features a Zynq™ UltraScale+™ MPSoC with a quad-core Arm® Cortex®-A53, dual-core Cortex-R5F real-time processors, and a Mali™-400 MP2 graphics processing unit based on 16nm FinFET+ LinuxPTP version is 3. Programmable Logic, I/O & Boot/Configuration. ZCU102 acts as the slave of 1588 and uses commands (“ptp4l -i eth0 -s -m”) to test, but we will get high values of master offset, frequency and path delay as a result. I change the patch as in system-user. Could you tell me where to find the previous release or how to proceed to be able to GEM3 ethernet with a Microblaze Now am going to connect ZC706 and ZCU102 via PCIe slot. I started by creating a project via the available 2021. -----lwIP TCP echo server ------. I am trying to implement PS EMIO ethernet as explained in xapp 1305/ 1306. Subscribe to the latest news from AMD. Hello All I am trying to implement an application where the PS Ethernet port of ZCU102 (Gem 3) is connected to PC and this data form PS Ethernet is forwarded to PL Ethernet of ZCU102 and the same is communicated to other ZCU102 board. 0 or rev D2 with production silicon; Monitor with DisplayPort or HDMI input supporting one of the following resolutions: 3840x2160 or; 1920x1080 or; 1280x720; Display Port cable (DP certified) or HDMI cable; Micro-USB cable, connected to laptop or desktop for the terminal emulator; Xilinx USB3 micro-B adapter Sep 5, 2023 · When I try to enable the 10g interface in Petalinux, I get this message: [ 69. U-Boot only sees PS GEM3 as eth0, from "mii device". No ethernet found. 2021. See page 41 of the ZCU102 schematics on page 41. 5. 79K AR#66367: 2015. 2). 168. I am also using the ps_pl_1g. . An ILA check shows the clock instant that corresponds to /dev/ptp0 gets updated when ptp4l starts running. However, it will be up to the customers to decide which module to use and we do not recommend a particular one. 1. This kit features a Zynq™ UltraScale+™ MPSoC with a quad-core Arm® Cortex®-A53, dual-core Cortex-R5F real-time processors, and a Mali™-400 MP2 graphics processing unit based on 16nm FinFET+ DMA reset timeout with 10G ethernet on ZCU102. 2 image generated with my hdf file (Vivado 2017. 10G between two ZCU102 boards works fine. 01. bat if you are using the ZCU102. I have downloaded the 1G PL Ethernet files from https Hello, is there any reference design (block design, etc. I'm attempting to migrate an existing petalinux 2020. ethernet eth1: XXV MAC block lock not complete! Cross-check the MAC ref clock configuration Ethernet interface is working great when i use "xilinx-zcu102-v2017. Board & Kit Accessories. I have a problem after bootstrap; i see continuosly link-up and link-down request operation printed out from the uart-dbg. 0: PCI bridge to [bus 01-0c] Communication between PS and PL ethernet of ZCU102. After that, the PCS/PMA status is correct even after booting with macb and xilinx-phy drivers compiled into the kernel, but the driver still thinks, that the link works at 10Mb/s (even though the PCS/PMA status shows 1Gb/s!) If you are using 40G Ethernet Subsystem, you can use the SFP cage on the ZCU102 board and use 4 identical SFP cables and connect to the link partner. I'm wondering if why ethtool doesn't show any details on the port? Can you have a look at the attached zip. Let me know if this helps. ls /dev/ output: clocks. Ethernet. But, i'm trying to make it works on my PetaLinux 2017. AR# 69640: Zynq UltraScale+ MPSoC ZCU102 評価キット - ZCU102 システムコントローラー GUI への信頼性の高い接続を確保する Number of Views 1. We want to confirm the TX/RX Checksum offloading is ethool for eth1 has ptp0 as hardware clock. Hi, I am running Petalinux on the ZCU102 with Xen. The ZCU102 can still fetch an IPv4 using DHCP, and ping but cannot utilize wget, SSH, SCP, etc. PNG. The design includes the PCS/PMA IP which is connected to an SFP port on the board. 0 PCI bridge: Xilinx Corporation Device d021. It runs correctly. 0 1. I set a server with iperf3 but if I try to set a EK-U1-ZCU102-G-ED is a Zynq UltraScale+ MPSoC ZCU102 evaluation kit with encryption disabled feature. EK-U1-ZCU102-G – Zynq UltraScale+ MPSoC ZCU102 XCZU9EG Zynq® UltraScale+™ FPGA + MCU/MPU SoC Evaluation Board from AMD. Dec 3, 2023 · Is it possible to configure ZCU102 board using ethernet similar to the way it is configured over JTAG or USB. 2-final. LinuxPTP version is 3. 5 netmask 255. To boot the ZCU102, I am using the images from Release 2020. 10G on ZCU111 in loopback works fine. > However, i couldn't find any reference design to use in order to implement functions, or even to saw how to DDR4 controlers (PS or PL) are configured (which is the part i'm interesting of). Ibra (Member) asked a question. You can find example projects on this link. **BEST SOLUTION** Hi @cinesyscks8 ,. there are some MPSoC example projects about 1G, 10G PL ethernet in ZCU102 Question According to UG1085, MPSoC's PL only has 100G Ethernet. 255. August 18, 2020 at 10:07 AM. TCP packets sent to port 6001 will be echoed back. Manufacturers Standard Package. dtsi as attached here. 5G Ethernet PCS/PMA IP. 1 Mask:255. 1G/10G/25G Switching Ethernet Subsystem IP version 2. I created a block design using PCS/PMA interface But Unable to ping the interface from PC in both baremetal and linux mode. The program waits indefinitely for PHY to complete auto negotiation. 4: ZCU102. Hello, I'm working with the ZCU102 Evaluation Board. To simply answer your question, both are a YES. We have stopped shipping ZCU102 ES2 boards and BSP since 2018. [ 39. Hello, I am trying to test the Internal loopback (local loopback) on ethernet port of Xilinx ZCU102 Eval Board. using GEM3 with a microblaze on ZCU102. 2 project to 2021. The ZCU102 evaluation kit enables designers to jumpstart designs for automotive, industrial, video, and communications applications. I want to access the GEM0 (SFP) Ethernet port. com > AuthorDate Thanks @shabbirk . The original post date was 2021-01-02. The Kit's ZCU102 Board supports all major peripherals and interfaces, enabling Feb 12, 2024 · Video 268190uoyil780 March 19, 2024 at 3:07 AM. So on the surface it appears the phyaddr being used for 2021. ethtool_1. 2 that I want to run on a network with each other. 1> of vivado. We are not seeing the ethernet being detected. 10G on ZCU102 in loopback works fine. I need the measurements of the pcb. 00000. How do i set the Ethernet PHY to loopback mode in Xilinx ZCU102 to send and receive a single frame. I am trying to use PS GEM3 and PL !G of ZCU102. Xilinx, ZCU102. The Kit's ZCU102 Board supports all major peripherals and interfaces, enabling I have been reading through the ZCU102 TRM about ethernet. 00 MHz (using the onboard CLK_125_P/N and routing it to a IBUFDS primitive to obtain "dclk") ZCU102 SFP Ethernet confusion. See full list on github. 1 day ago · Scalable Portfolio of Adaptable MPSoCs. Yocto Settings → YOCTO_MACHINE_NAME Double click on the batch file that is appropriate to your hardware, for example, double-click build-zcu102. I use the default hardware of the bsp to build the petalinux project and I run it with an SD card. Ease of use enhancements in IPI, DFX, Debug and Simulation. 1, Vivado 2017. 3. you can do this by writing into the management registers. simek@xilinx. 4 for our design to be run on ZCU102 board. Control and Status Vectors. Regards, Sai Vikas T R. This kit features a Zynq™ UltraScale+™ MPSoC with a quad-core Arm® Cortex®-A53, dual-core Cortex-R5F real-time processors, and a Mali™-400 MP2 graphics Dec 15, 2020 · Figure 1: Zynq UltraScale+ MPSoC Ethernet Interface Note: The PS-GEM3 is always tied to the TI RGMII PHY on the ZCU102 evaluation board. I do have other versions of vivado like 19,20 and 21. 11. Please share anymore suggestions or any other possible ways to configure the ZCU102 board over ethernet. I check this by this command. Enabling PTP with ZCU102 MCDMA AXI Ethernet prevents internet connectivity. Hello All. The setup image is attached. root@farzian:~ # echo 1 > /sys/bus/pci/rescan. 1: Net: ZYNQ GEM: ff0b0000, phyaddr 5, interface rgmii-id. EK-U1-ZCU102-G-ED is a Zynq UltraScale+ MPSoC ZCU102 evaluation kit with encryption disabled feature. Sorry for bothering again but I already have an evaluation license to run the AXI 1G/2. Then we started with $ petalinux-config. Here is what I have done: I run . 1 on the ZCU102 board and have started with a baseline to ensure things work as expected. Built on a common real-time processor and programmable logic equipped platform, three distinct variants include dual root@xilinx-zcu102-2020_1:~ # lspci. AXI Ethernet Subsystem is the soft IP which you can generate it on PL. The LogiCORE™ IP 10G/25G Ethernet solution provides a 10 Gigabit or 25 Gigabit per second (Gbps) Ethernet Media Access Controller integrated with a PCS/PMA in BASE-R/KR modes or a standalone PCS/PMA in BASE-R/KR modes. Pricing and Availability on millions of electronic components from Digi-Key Electronics. One thing to be wary of is that you either have to apply the clocking patch like or change the reference frequency to 156. lo Link encap:Local Loopback. As soon as I mount the partitions (from the image, before writing to the SD Card) in a Linux install and do an FSCK, then it finds an enormous number errors after fixing them and copy the install to the SD Card and boot, there is no issue with eth0. To detect PL Ethernet in ZCU102. there is no 1G or 10G Eth in PL. PS Gem3 of ZCU102 is successfully up, however, when I am trying to add the follwoing in system-user. Hello everybody, I'm trying to make PCI-E work on ZCU102, but so far not too much luck. Of course after that change, you have to set the ZCU102 Si5328 MGT Clock Frequency to 125MHz after the ZCU102 power-up. However, /dev/ptp1 never gets updated. ZCU102 Petalinux 2021. 2 with Vivado 2018. In order to make some tests, my company bought an evaluation board, ZCU102. 161455] xilinx_axienet 80010000. My Vivado installation is 2018. Is it possible to SSH over the standard ethernet port? Logging in vai UART I could set: ifconfig eth0 192. 3 and ZCU102 Zynq Ultrascale board. Hi, I am using Vivado 2018. Order today, ships today. ethernets: eth0: addresses: - 192. I need to use PL based 1G Ethernet on Zynq Ultrascale \+ MPSoC platform for ZCU102 evaluation board with Petalinux version 2018. 5G Ethernet Subsystem" IP Core only on the PL side of the KCU105 board I have. I would like to setup my board to have 2x 1G ethernet ports (one for input, one for output, un-synchronized). c following as to point to GEM3: ZCU102 评估套件可帮助设计人员快速启动面向汽车、工业、视频以及通信应用的设计。. I am not sure if I need the "processor features/mode" available in the AXI 1G Ethernet Subsystem. Start PHY autonegotiation. com EK-U1-ZCU102-G is a Zynq UltraScale+ MPSoC ZCU102 evaluation kit. This kit features a Zynq UltraScale+ MPSoC device with a quad-core ARM Cortex-A53, dual-core Cortex-R5 real-time processors, and a Mali-400 MP2 graphics processing unit based on Xilinx's 16nm FinFET+ programmable logic fabric. 25 MHz as expected. When I try to build the design using the included script, it errors out because "This script was generated using Vivado<2017. As you are mentioning GEM2 and GEM3 connected to GT lanes, for such configurations, refer to this link : 69769 - PetaLinux - Zynq MPSoC PS-GTR SGMII - fixed link support patch (xilinx. zcu102 hello World. if you have an example design, please share. ethernet eth1: __axienet_device_reset: DMA reset timeout! [ 39. 2 is now available for download: Meeting Fmax targets. ethernet: couldn't find phy i/f". 25 MHz. 4. 5G Ethernet Subsystem IP reference design. MTU | TCP Tx |TCP Rx |UDP Tx |UDP Rx | 1500 |2. Run Vivado and open the project that was just created. What is confusing is that the values used for the pull-up and pull-down strapping resistors on the DP838671IR strapping pins in no way resemble Texas Instruments&#39 Hello, i'm work on a zcu102 eval board rev 1. I also changed the configuration to enable a dynamic IP and connected the board directly to the router. 25MHz in the Ethernet core, since that's what the ZCU102 defaults to. AMD / Xilinx MPSoC ZCU102 Evaluation Kit features a Zynq UltraScale+ MPSoC device with a quad-core Arm® Cortex-A53, dual-core Cortex-R5 real-time processors, and a Mali-400 MP2 graphics processing unit based on AMD / Xilinx's 16nm FinFET+ programmable logic fabric. A very late answer, but I have the same issue. The PHY will be inside the PHY module you insert into the SFP cage. From concept to product production, AMD FPGA and SoC boards, kits, and modules, provide you with an out-of-the box hardware platform to both speed your development time and enhance your productivity. 4 Gbps |2Gbps |800 | The results I get are as follows. By inspecting debug LED status, the IP start with a 10G configuration. hello, im new to xilinx and im working with vivado 2019. 4 PetaLinux ZCU102 BSP を含む ZCU102 RevB ボードで MIO イーサネットが機能しない Dec 15, 2020 · Figure 1: Zynq UltraScale+ MPSoC Ethernet Interface Note: The PS-GEM3 is always tied to the TI RGMII PHY on the ZCU102 evaluation board. The Petalinux project was created from the zcu102 BSP downloaded from Xilinx. It seems that the image is corrupt. 2: Other Details Hi, I am working to implement an Ethernet link on ZCU102, by using the 1G/10G/25G Switching Ethernet Subsystem IP version 2. EK-U1-ZCU102-G is a Zynq UltraScale+ MPSoC ZCU102 evaluation kit. dtsi file from. Here's our situation now -. With this I was able to list some PCI Ethernet card, but I needed to reboot to "see" it at lspci. Attached below is a sequence showing the eth1 being set up from the console. 2 version is wrong. (I have reference documents XAPP1305 Ethernet Subsystem) I create a project to implement loopback on 2 SFP+ ports of the board, with IP Core Trans_Rev_Data_10G is responsible for pushing ethernet packet II to Port 0 and loopback to port 2 (image The ZCU102 Si570 MGT clock is set with SCUI to 156. I ran the "AXI 1G/2. Zynq™ UltraScale+™ MPSoC devices provide 64-bit processor scalability while combining real-time control with soft and hard engines for graphics, video, waveform, and packet processing. I am using the ZCU102 evaluation board (XCZU9EG-FFVB1156) and I am trying to set up the 2x2 SFP cage via the transceiver to handle Ethernet (with suitable external SFP adapter). I figure I will make use of the SFP\+ cages provided and use one as an input, and one as an output. evaluation board. Find Your Board. When the bitstream is successfully generated, select File September 30, 2019 at 1:53 PM. I did ifconfig and I only see loopback and SIT ports. In order to implement MIO application, I changed platform_config. Hi all, I am trying to transmit packets via 1GE/SFP on the ZCU102. $3,570. 2. Especially the position of the board connectors on the Evaluation Boards 267174aliemgemg March 7, 2024 at 2:33 PM. 1 bsp for the ZCU102, editing only the static IP address (instead of DHCP). DTG Settings → MACHINE_NAME, set that to zcu102-rev1. June 17, 2020 at 10:12 AM. 4) 10GbE working on my ZCU102 board (rev 1. Just like here, I want to drive the phy chip on the board in ZCU102 and use the RJ45 input (RJ45 is not necessary, it can be done using sfp) and I want No Ethernet in PetaLinux 2017. GT RefClk = 156. inet addr:127. At this moment, I have the IP core configured for 1000BASE-X with "processor features" disabled, but I am not 100% sure whether I need the features available in processor mode or not. gateway4: 192. UG1087 is the register space which is for Gigabit Ethernet Controller (GEM) in PS. Ethernet interface is working great when i use "xilinx-zcu102-v2017. 00. 2), we are no longer able to connect to the ZCU102 using SSH. How can it configure and implement 1G and 10G Ethernet in PL? May 31, 2023 · PMU-FW is not running, certain applications may not be supported. From the images, you can see that one hardware clock has been attached to both ethernet ports. 25 MHz (using the onboard Programmable User MGT Clock default freq) GT DRP Clock = 125. After Enabling 1588 on the AXI 1G/2. 1 and zcu102 rev 1. 00:00. Core configuration: 10G Ethernet MAC \+ PCS/PMA 64-bit - BASE-R. bp ra vl ck dn oy gf li cu ez